White Electronic Designs
REFRESH cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to t
RAS
and may remain
in self refresh mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock
is defined as a signal cycling within timing constraints
specified for the clock pin) prior to CKE going back
HIGH. Once CKE is HIGH, the SDRAM must have NOP
commands issued (a minimum of two clocks) for t
XSR
,
because time is required for the completion of any internal
refresh in progress.
Upon exiting the self refresh mode, AUTO REFRESH
commands must be issued as both SELF REFRESH and
AUTO REFRESH utilize the row refresh counter.
*Self Refresh available in commercial and industrial temperatures only.
WEDPN8M64V-XB2X
January 2005
Rev. 2
9
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