WCMA1008C1X
128K x 8 Static RAM
Features
• Voltage Range
—
4.5V–5.5V
• Low active power
— Typical active current: 6 mA @ f = f
max
(70 ns speed)
• Low standby current
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
1
, CE
2
, and OE fea-
tures
• CMOS for optimum speed/power
(OE), and three-state drivers. This device has an automatic
power-down feature that reduces power consumption by more
than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through
I/O
7
) is then written into the location specified on the address
pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip En-
able 1 (CE
1
) and Output Enable (OE) LOW while forcing Write
Enable (WE) and Chip Enable 2 (CE
2
) HIGH. Under these
conditions, the contents of the memory location specified by
the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW)
The WCMA1008C1X is available in a standard 32-pin
450-mil-wide body width SOIC and 32-pin TSOP type I.
Functional Description
The WCMA1008C1X is a high-performance CMOS static
RAM organized as 128K words by 8 bits. Easy memory expan-
sion is provided by an active LOW Chip Enable (CE
1
), an ac-
tive HIGH Chip Enable (CE
2
), an active LOW Output Enable
Logic Block Diagram
Pin Configuration
Top View
SOIC
A
17
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
INPUT BUFFER
A0
A1
A2
A3
A4
A5
A6
A7
A8
ROW DECODER
I/O 0
I/O 1
SENSE AMPS
I/O 2
I/O 3
I/O 4
I/O 5
POWER
DOWN
512x 256x 8
ARRAY
CE1
CE2
WE
OE
COLUMN
DECODER
A9
A 10
A 11
A 12
A 13
A 14
A 15
A 16
I/O 6
I/O 7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
A
18
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
TSOP I
Top View
(not to scale)
OE
A
10
CE
1
I/O
7
I/O
I/O
6
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
April 5, 2002
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
