1
WCMA1016U4X
64K x 16 Static RAM
Features
• High Speed
— 55ns and 70ns availability
•
Low voltage range
—
2.7V−3.6V
• Ultra-low active power
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
and BHE are HIGH). The input/output pins (I/O
0
through I/O
15
)
are placed in a high-impedance state when: deselected (CE
HIGH), outputs are disabled (OE HIGH), both Byte High En-
able and Byte Low Enable are disabled (BHE, BLE HIGH), or
during a write operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
15
). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
15
).
Reading from the device is accomplished by taking Chip En-
able (CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE) is LOW,
then data from memory will appear on I/O
8
to I/O
15
. See the
Truth Table at the back of this data sheet for a complete de-
scription of read and write modes.
The WCMA1016U4X is available in a 48-ball FBGA package.
Functional Description
The WCMA1016U4X is a high-performance CMOS static
RAM organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra-low active current.
This device s ideal for portable applications such as cellular
telephones. The device also has an automatic power-down
feature that significantly reduces power consumption by 99%
when addresses are not toggling. The device can also be put
into standby mode when deselected (CE HIGH or both BLE
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
64K x 16
RAM Array
2048 X 512
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
BHE
BLE
A
11
A
12
A
13
Power - Down
Circuit
A
14
A
15