1*WCMA2016U4B
WCMA2016U4B
128K x 16 Static RAM
Features
• High Speed
— 55ns and 70ns speed availability
• Low Voltage range:
— 2.7V-3.3V
• Ultra-low active power
— Typical active current: 1.5 mA @ f = 1MHz
•
•
•
•
— Typical active current: 7 mA @ f = f
max
Low standby power
Easy memory expansion with CE and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
be put into standby mode reducing power consumption by
more than 99% when deselected (CE HIGH or both BLE and
BHE are HIGH). The input/output pins (I/O
0
through I/O
15
) are
placed in a high-impedance state when: deselected ( E
C
HIGH), outputs are disabled (OE HIGH), both Byte High En-
able and Byte Low Enable are disabled (BHE, BLE HIGH), or
during a write operation (CE LOW, and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE ) is LOW, then data from I/O pins (I/O
0
through I/O
7
), is
written into the location specified on the address pins (A
0
through A
16
). If Byte High Enable (BHE ) is LOW, then data
from I/O pins (I/O
8
through I/O
15
) is written into the location
specified on the address pins (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
0
to I/O
7
. If Byte High Enable (BHE ) is
LOW, then data from memory will appear on I/O
8
to I/O
15
. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The WCMA2016U4B is available in a 48-ball FBGA package.
Functional Description
The WCMA2016U4B is a high-performance CMOS static
RAMs organized as 128K words by 16 bits. These devices
feature advanced circuit design to provide ultra-low active cur-
rent. This device is ideal for portable applications such as cel-
lular telephones. The devices also have an automatic pow-
er-down feature that significantly reduces power consumption
by 80% when addresses are not toggling. The device can also
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1 0
RO W DE CO DER
128K x 16
RAM Array
2048 x 1024
SENSE AMPS
I/O
0
– I/O
7
I/O
8
– I/O
15
COLUMN DECODER
BHE
WE
CE
OE
BLE
CE
BHE
BLE
A
11
A
12
A
13
A
14
A
15
Powe r
-
Down
Circuit
A
16
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
