ADVANCE INFORMATION
WCMC8016V9X
8Mb (512K x 16) Pseudo Static RAM
Features
• Wide voltage range:
2.70V–3.30V
• Access Time: 70ns
• Ultra-low active power
— Typical active current: 2.0mA @ f = 1 MHz
•
•
•
•
•
— Typical active current: 11mA @ f = f
max
Ultra low standby power
Easy memory expansion with CE, CE
2
, and OE features
Automatic power-down when deselected
CMOS for optimum speed/power
Offered in a 48 Ball BGA Package
This is ideal for providing More Battery Life
®
(MoBL
®
) in
portable applications such as cellular telephones. The device
can be put into standby mode reducing power consumption by
more than 99% when deselected using CE LOW, CE
2
HIGH
or both BHE and BLE are HIGH. The input/output pins (I/O
0
through I/O
1 5
) are placed in a high-impedance state when:
deselected (CE HIGH, CE
2
LOW OE is deasserted HIGH), or
during a write operation (Chip Enabled and Write Enable WE
LOW). The device also has an automatic power-down feature
that significantly reduces power consumption by 99% when
addresses are not toggling even when the chip is selected
(Chip Enable CE LOW, CE
2
HIGH and both BHE and BLE are
LOW). Reading from the device is accomplished by asserting
the Chip Enables (
CE LOW and CE
2
HIGH) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.
If Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins will appear on I/O
0
to
I/O
7
. If Byte High Enable ( HE) is LOW, then data from
B
memory will appear on I/O
8
to I/O
1 5
. See the Truth Table for a
complete description of read and write modes
Functional Description
[1]
The WCMC8016V9X is a high-performance CMOS pseudo
static RAM organized as 512K words by 16 bits that supports
an asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
512K x 16
RAM Array
1T
SENSE AMPS
I/O
0
–I/O
7
I/O
8
–I/O
15
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
BHE
WE
OE
BLE
CE
2
CE
Pow
-
er Down
Circuit
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress .com.
WeidaSemiconductor, Inc.
38-14026
Revised August 2003
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
