欢迎访问ic37.com |
会员登录 免费注册
发布采购

WCMS0808U1X-TF70 参数 Datasheet PDF下载

WCMS0808U1X-TF70图片预览
型号: WCMS0808U1X-TF70
PDF下载: 下载PDF文件 查看货源
内容描述: 32K x 8静态RAM [32K x 8 Static RAM]
分类和应用:
文件页数/大小: 10 页 / 222 K
品牌: WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
 浏览型号WCMS0808U1X-TF70的Datasheet PDF文件第2页浏览型号WCMS0808U1X-TF70的Datasheet PDF文件第3页浏览型号WCMS0808U1X-TF70的Datasheet PDF文件第4页浏览型号WCMS0808U1X-TF70的Datasheet PDF文件第5页浏览型号WCMS0808U1X-TF70的Datasheet PDF文件第6页浏览型号WCMS0808U1X-TF70的Datasheet PDF文件第7页浏览型号WCMS0808U1X-TF70的Datasheet PDF文件第8页浏览型号WCMS0808U1X-TF70的Datasheet PDF文件第9页  
S0808U1X
WCMS0808U1X
32K x 8 Static RAM
Features
• Low voltage range:
2.7V
3.6V
• Low active power and standby power
• Easy memory expansion with CE and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• CMOS for optimum speed/power
reducing the power consumption by over 99% when deselect-
ed. The WCMS0808U1X is available in the 450-mil-wide
(300-mil body width) narrow SOIC and TSOP.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When CE and WE inputs
are both LOW, data on the eight data input/output pins (I/O
0
through I/O
7
) is written into the memory location addressed by
the address present on the address pins (A
0
through A
14
).
Reading the device is accomplished by selecting the device
and enabling the outputs, CE and OE active LOW, while WE
remains inactive or HIGH. Under these conditions, the con-
tents of the location addressed by the information on address
pins are present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.
Functional Description
The WCMS0808U1X is composed of a high-performance
CMOS static RAM organized as 32K words by 8 bits. Easy
memory expansion is provided by an active LOW chip enable
(CE) and active LOW output enable (OE) and three-state driv-
ers. These devices have an automatic power-down feature,
Logic Block Diagram
Pin Configurations
Narrow
SOIC
Top View
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
A
4
A
3
A
2
A
1
OE
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
INPUTBUFFER
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
CE
WE
OE
A
14
A
13
A
12
A
11
A
1
A
0
ROW DECODER
I/O
0
I/O
1
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
512x512
ARRA
Y
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
OE
A
1
A
2
A
3
A
4
WE
V
CC
A
5
A
6
A
7
A
8
A
9
A
10
A
11
22
23
24
25
26
27
28
1
2
3
4
5
6
7
21
20
19
18
17
16
15
14
13
12
11
10
9
8
TSOP I
Top View
(not to scale)
A
0
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
14
A
13
A
12