Y7C1350B
WCSN0436V1P
128Kx36 Pipelined SRAM with NoBL™ Architecture
Features
• Pin compatible and functionally equivalent to ZBT™
devices IDT71V546, MT55L128L36P, and MCM63Z736
• Supports 166-MHz bus operations with zero wait states
— Data is transferred on every clock
• Internally self-timed output buffer control to eliminate
the need to use OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• 128K x 36 common I/O architecture
• Single 3.3V power supply
• Fast clock-to-output times
— 3.5 ns (for 166-MHz device)
— 3.8 ns (for 150-MHz device)
— 4.0 ns (for 143-MHz device)
— 4.2 ns (for 133-MHz device)
— 5.0 ns (for 100-MHz device)
•
•
•
•
•
•
— 7.0 ns (for 80-MHz device)
Clock Enable (CEN) pin to suspend operation
Synchronous self-timed writes
Asynchronous output enable
JEDEC-standard 100 TQFP package
Burst Capability—linear or interleaved burst order
Low standby power (17.325 mW max.)
Functional Description
The WCSN0436V1P is a 3.3V, 128K by 36 synchronous-pipe-
lined Burst SRAM designed specifically to support unlimited
true back-to-back Read/Write operations without the insertion
of wait states. The WCSN0436V1P is equipped with the ad-
vanced No Bus Latency™ (NoBL™) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.The WCSN0436V1P is
pin/functionally compatible to ZBT SRAMsIDT71V546,
MT55L128L36P, and MCM63Z736.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 3.5 ns (166-MHz device).
Write operations are controlled by the four Byte Write Select
(BWS
[3:0]
) and a Write Enable (WE) input. All writes are con-
ducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank se-
lection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram
CLK
D
Data-In REG.
CE Q
36
17
CONTROL
and WRITE
LOGIC
17
128Kx36
MEMORY
ARRAY
36
36
ADV/LD
A
[16:0]
CEN
CE
1
CE2
CE3
WE
BWS
[3:0]
MODE
CLK
OOUTPUT
REGISTERS
and LOGIC
36
DQ
[31:0]
DP
[3:0]
OE
.
Selection Guide
-166
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
.
.
-150
3.8
375
5
-143
4.0
350
5
-133
4.2
300
5
-100
5.0
250
5
-80
7.0
200
5
3.5
Commercial
Commercial
400
5
Document#: 38-05246
Revised Jan 06,2002
WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
