WILLAS
SL12-N THRU SL14-N
DTC114EKA /DTC114ECA/DTC114ESA
DIGITAL TRANSISTOR (NPN)
Low VF Chip S
Digital Transistors (Built-in Resistors)
1.0A Surface Mount Schottky Barrier
Rectifiers - 20V-40V
DTC114EM/DTC114EE/DTC114EUA
Package outline
Features
•
Batch process design, excellent power dissipation offers
·Equivalent
Circuit
better reverse leakage current and thermal resistance.
FEATURES
•
Low profile surface mounted application in order to
optimize board space.
Built-in bias resistors enable the configuration of an inverter circuit
Low power loss, high efficiency.
•
without connecting external input resistors(see equivalent circuit)
•
High current capability, very low forward voltage drop.
•
The bias resistors consist of thin-film resistors with complete isolation
High surge capability.
Guardring for overvoltage protection.
•
to allow positive biasing of the input.They also have the advantage of
Very
completely eliminating parasitic
•
almost
tiny plastic SMD package.
effects
•
Ultra high-speed switching.
•
Only the on/off conditions need to be set for
silicon junction.
device design easy
Silicon epitaxial planar chip, metal
operation, making
SOD
0.106
0.091
RoHS product for packing code suffix "G"
Halogen free product for packing code suffix "H"
PIN CONNENCTIONS and MARKING
Mechanical data
DTC114EM
SOT-723
DTC114EE
SOT-523
0.016(0.4) Typ.
•
Epoxy : UL94-V0 rated flame retardant
•
Case : Molded plastic, SOD-323-L
1. IN
2. GND
•
Terminals :Plated terminals, solderable per MIL-STD-750,
3. OUT
MARKING:24
Method 2026
MARKING:24
1. IN
2. GND
3. OUT
Dimensions in inche
•
Polarity : Indicated by cathode band
SOT-323
•
DTC114EUA
Position : Any
Mounting
•
Weight : Approximated 0.008 gram
1. IN
2. GND
3. OUT
DTC114EKA
SOT-23-3L
1. IN
2. GND
3. OUT
Maximum ratings
(AT
PARAMETER
DTC114ECA
Forward rectified current
Forward surge current
Reverse
MARKING:24
current
Thermal resistance
Diode junction capacitance
Storage temperature
2012-05
MARKING:24
T
A
=25
o
C unless otherwise noted)
SOT-23
MARKING:24
CONDITIONS
DTC114ESA
TO-92S
Symbol
I
O
I
FSM
I
R
R
θJA
See Fig.2
1. IN
8.3ms
3. OUT
1. GND
single half sine-wave superimposed on
2. GND
load (JEDEC methode)
2. OUT
rate
3. IN
O
V
R
= V
RRM
T
J
= 25 C
Junction to ambient
f=1MHz and applied 4V DC reverse voltage
C,Mar,2012
C
J
T
STG
WILLAS ELECTRONIC CORP.
WILLAS [ WILLAS ELECTRONIC CORP ]
