Preliminary W24256
32K
×
8 CMOS STATIC RAM
GENERAL DESCRIPTION
The W24256 is a normal speed, very low power CMOS static RAM organized as 32768
×
8 bits that
operates on a single 5-volt power supply. This device is manufactured using Winbond's high
performance CMOS technology.
FEATURES
•
Low power consumption:
•
Access time: 70 nS (max.)
•
Active :300 mW
Standby :250
µW
•
Single 5V power supply
•
Fully static operation
•
All inputs and outputs directly TTL compatible
•
•
•
•
Three-state outputs
Battery back-up operation capability
Data retention voltage: 2V (min.)
Packaged in 28-pin 600 mil DIP, 330 mil SOP
and standard type one TSOP (8 mm
×
13.4
mm)
PIN CONFIGURATIONS
BLOCK DIAGRAM
CLK GEN.
A12
A14
A2
R
O
W
D
E
C
O
D
E
R
PRECHARGE CKT.
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28-pin
DIP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
DD
WE
A13
A8
A9
A11
OE
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
A3
A4
A5
A6
A7
A13
I/O1
I/O8
CORE CELL ARRAY
512 ROWS
64 X 8 COLUMNS
DATA
CNTRL.
CLK
GEN.
I/O CKT.
COLUMN DECODER
WE
CS
OE
A11 A10 A1 A0 A8 A9
PIN DESCRIPTION
OE
A11
A9
A8
A13
WE
V
DD
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CS
I/O8
I/O7
I/O6
I/O5
I/O4
V
SS
I/O3
I/O2
I/O1
A0
A1
A2
SYMBOL
A0−A14
I/O1−I/O8
CS
WE
28-pin
TSOP
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Select Input
Write Enable Input
Output Enable Input
Power Supply
Ground
OE
V
DD
V
SS
-1-
Publication Release Date: October 1999
Revision A1
WINBOND [ WINBOND ]
