W25P243A
FUNCTIONAL DESCRIPTION
The W25P243A is a synchronous-burst pipelined SRAM designed for use in high-end personal
computers. It supports two burst address sequences for Intel™ systems (Interleaved mode) and linear
mode, which can be controlled by the LBO pin. The burst cycles are initiated by ADSP or ADSC
and the burst counter is incremented whenever ADV is sampled low.
BURST ADDRESS SEQUENCE
INTEL SYSTEM ( LBO = V
DD
)
A[1:0]
External Start Address
Second Address
Third Address
Fourth Address
00
01
10
11
A[1:0]
01
00
11
10
A[1:0]
10
11
00
01
A[1:0]
11
10
01
00
LINEAR MODE ( LBO = V
SS
)
A[1:0]
00
01
10
11
A[1:0]
01
10
11
00
A[1:0]
10
11
00
01
A[1:0]
11
00
01
10
The device supports several types of write mode operations. BWE and BW [8:1] support individual
byte writes. The BE [7:0] signals can be directly connected to the SRAM BW [8:1]. The GW signal is
used to override the byte enable signals and allows the cache controller to write all bytes to the
SRAM, no matter what the byte write enable signals are. The various write modes are indicated in the
Write Table below. Note that in pipelined mode, the byte write enable signals are not latched by the
SRAM with addresses but with data. In pipelined mode, the cache controller must ensure the SRAM
latches both data and valid byte enable signals from the processor.
TRUTH TABLE
CYCLE
Unselected
Unselected
Unselected
Unselected
Unselected
Begin Read
Begin Read
Continue Read
Continue Read
Continue Read
Continue Read
Suspend Read
Suspend Read
Suspend Read
Suspend Read
ADDRESS
USED
No
No
No
No
No
External
External
Next
Next
Next
Next
Current
Current
Current
Current
CE1
1
0
0
0
0
0
0
X
X
1
1
X
X
1
1
CE2
X
X
0
X
0
1
1
X
X
X
X
X
X
X
X
CE3
X
1
X
1
X
0
0
X
X
X
X
X
X
X
X
ADSP
X
0
0
1
1
0
1
1
1
X
X
1
1
X
X
ADSC
0
X
X
0
0
X
0
1
1
1
1
1
1
1
1
ADV
X
X
X
X
X
X
X
0
0
0
0
1
1
1
1
OE
DATA
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
D-Out
Hi-Z
D-Out
Hi-Z
D-Out
Hi-Z
D-Out
WRITE*
X
X
X
X
X
X
Read
Read
Read
Read
Read
Read
Read
Read
Read
X
X
X
X
X
X
X
1
0
1
0
1
0
1
0
-4-
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