欢迎访问ic37.com |
会员登录 免费注册
发布采购

W25Q128BV 参数 Datasheet PDF下载

W25Q128BV图片预览
型号: W25Q128BV
PDF下载: 下载PDF文件 查看货源
内容描述: 具有双路和四路SPI 3V 128M位串行闪存 [3V 128M-BIT SERIAL FLASH MEMORY WITH DUAL AND QUAD SPI]
分类和应用: 闪存
文件页数/大小: 74 页 / 756 K
品牌: WINBOND [ WINBOND ]
 浏览型号W25Q128BV的Datasheet PDF文件第1页浏览型号W25Q128BV的Datasheet PDF文件第2页浏览型号W25Q128BV的Datasheet PDF文件第3页浏览型号W25Q128BV的Datasheet PDF文件第4页浏览型号W25Q128BV的Datasheet PDF文件第6页浏览型号W25Q128BV的Datasheet PDF文件第7页浏览型号W25Q128BV的Datasheet PDF文件第8页浏览型号W25Q128BV的Datasheet PDF文件第9页  
W25Q128BV
1. GENERAL DESCRIPTION
The W25Q128BV (8M-bit) Serial Flash memory provides a storage solution for systems with limited
space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash
devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP)
and storing voice, text and data. The device operates on a single 2.7V to 3.6V power supply with current
consumption as low as 4mA active and 1µA for power-down.
The W25Q128BV array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes
can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128
(32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128BV
has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater
flexibility in applications that require data and parameter storage. (See Figure 2.)
The W25Q128BV supports the standard Serial Peripheral Interface (SPI), and a high performance
Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1
(DO), I/O2 (/WP), and I/O3 (/HOLD). SPI clock frequencies of up to 104MHz are supported allowing
equivalent clock rates of 208MHz (104MHz x 2) for Dual Output and 280MHz (70MHz x 4) for Quad SPI
when using the Fast Read Quad SPI instructions. These transfer rates can out perform standard
Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient
memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP
(execute in place) operation.
A Hold pin, Write Protect pin and programmable write protection, with top, bottom or complement array
control, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer
and device identification with a 64-bit Unique Serial Number.
2. FEATURES
Family of SpiFlash Memories
– W25Q128BV: 128M-bit/16M-byte
– 256-byte per programmable page
– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold
– Dual SPI: CLK, /CS, IO
0
, IO
1
, /WP, /Hold
– Quad SPI: CLK, /CS, IO
0
, IO
1
, IO
2
, IO
3
Highest Performance Serial Flash
– 104/70MHz Dual Output/Quad SPI clocks
– 208/280MHz equivalent Dual /Quad SPI
– 35MB/S continuous data transfer rate
– Up to 5X that of ordinary Serial Flash
(1)
– More than 100,000 erase/program cycles
– More than 20-year data retention
Efficient “Continuous Read Mode”
– Low Instruction overhead
– Continuous Read with 8/16/32/64-Byte Wrap
– As few as 8 clocks to address memory
– Allows true XIP (execute in place) operation
– Outperforms X16 Parallel Flash
Low Power, Wide Temperature Range
– Single 2.7 to 3.6V supply
– 4mA active current, <1µA Power-down current
– -40°C to +85°C operating range
Flexible Architecture with 4KB sectors
– Uniform Sector/Block Erase (4K/32K/64K-Byte)
– Program one to 256 bytes
– Erase/Program Suspend & Resume
Advanced Security Features
– Software and Hardware Write-Protect
– Top/Bottom, 4KB complement array protection
– Lock-Down and OTP array protection
– 64-Bit Unique Serial Number for each device
– Discoverable Parameters (SFDP) Register
– 3X256-Byte Security Registers with OTP locks
– Volatile & Non-volatile Status Register Bits
Space Efficient Packaging
– 8-pad WSON 8x6-mm
– 16-pin SOIC 300-mil
– 24-ball TFBGA 8x6-mm
– Contact Winbond for KGD and other options
Note 1: More than 100k Block Erase/Program cycles for Industrial and Automotive temperature; more than 10k full
chip Erase/Program cycles tested in compliance with AEC-Q100.
-5-
Publication Release Date: April 01, 2011
Revision E