W28V400B/T
Word/Byte Write Command
Word/byte write is executed by a two-cycle command sequence. Word/byte write setup (standard 40H
or alternate 10H) is written, followed by a second write that specifies the address and data (latched on
the rising edge of #WE). The WSM then takes over, controlling the word/byte write and write verify
algorithms internally. After the word/byte write sequence is written, the device automatically outputs
status register data when can be read (see Figure 6). The CPU can detect the completion of the
word/byte write event by analyzing the RY/#BY pin or status register bit SR.7.
When word/byte write is complete, status register bit SR.4 should be checked. If word/byte write error
is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s
that do not successfully write to "0"s. The CUI remains in read status register mode until it receives
another command.
Reliable word/byte writes can only occur when V
DD
= V
DD1/2/3/4
and V
PP
= V
PPH1/2/3
. In the absence of
this high voltage, memory contents are protected against word/byte writes. If word/byte write is
attempted while V
PP
≤
V
PPLK
, status register bits SR.3 and SR.4 will be set to "1". Successful word/byte
write for boot blocks requires that the corresponding if set, that #WP = V
IH
or #RESET = V
HH
. If
word/byte write is attempted to boot block when the corresponding #WP= V
IL
or #RESET= V
IH
, SR.1
and SR.4 will be set to "1". Word/byte write operations with V
IH
< #RESET < V
HH
produce spurious
results and should not be attempted.
Block Erase Suspend Command
The Block Erase Suspend command allows block-erase interruption to read or word/byte write data in
another block of memory. Once the block-erase process starts, writing the Block Erase Suspend
command requests that the WSM suspend the block erase sequence at a predetermined point in the
algorithm. The device outputs status register data when read after the Block Erase Suspend
command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase
operation has been suspended (both will be set to "1"). RY/#BY will also transition to V
OH
.
Specification t
WHRH2
defines the block erase suspend latency.
At this point, a Read Array command can be written to read data from blocks other than that which is
suspended. A Word/Byte Write command sequence can also be issued during erase suspend to
program data in other blocks. Using the Word/Byte Write Suspend command (see Word/Byte Write
Suspend Command section), a word/byte write operation can also be suspended. During a word/byte
write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/#BY
output will transition to V
OL
. However, SR.6 will remain "1" to indicate block erase suspend status.
The only other valid commands while block erase is suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will
continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and
RY/#BY will return to V
OL
.
After the Erase Resume command is written, the device automatically
outputs status register data when read (see Figure 7). V
PP
must remain at V
PPH1/2/3
(the same V
PP
level
used for block erase) while block erase is suspended. #RESET must also remain at V
IH
or V
HH
(the
same #RESET level used for block erase). #WP must also remain at V
IL
or V
IH
(the same #WP level
used for block erase). Block erase cannot resume until word/byte write operations initiated during
block erase suspend have completed.
- 15 -
Publication Release Date: April 11, 2003
Revision A4
WINBOND [ WINBOND ]
