W39V040FA
Hardware Data Protection
The integrity of the data stored in the W39V040FA is also hardware protected in the following ways:
(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.
(2) V
DD
Power Up/Down Detection: The programming and read operation are inhibited when V
DD
is
less than 1.5V typical.
(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This prevents
inadvertent writes during power-up or power-down periods.
(4) V
DD
power-on delay: When V
DD
has reached its sense level, the device will automatically time-out
5 mS before any write (erase/program) operation.
Data Polling (DQ
7
)- Write Status Detection
The W39V040FA includes a data polling feature to indicate the end of a program or erase cycle.
When the W39V040FA is in the internal program or erase cycle, any attempts to read DQ
7
of the last
byte loaded will receive the complement of the true data. Once the program or erase cycle is
completed, DQ
7
will show the true data. Note that DQ
7
will show logical "0" during the erase cycle,
and when erase cycle has been completed it becomes logical "1" or true data.
Toggle Bit (DQ
6
)- Write Status Detection
In addition to data polling, the W39V040FA provides another method for determining the end of a
program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ
6
will
produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between
0's and 1's will stop. The device is then ready for the next operation.
Register
There are three kinds of registers on this device, the General Purpose Input Registers, the Block Lock
Control Registers and Product Identification Registers. Users can access these registers through
respective address in the 4Gbytes memory map. There are detail descriptions in the sections below.
General Purpose Inputs Register
This register reads the FGPI[4:0] pins on the W39V040FA.This is a pass-through register which can
read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value.
GPI Register Table
BIT
7
−
5
4
3
2
1
0
Reserved
Read FGPI4 pin status
Read FGPI3 pin status
Read FGPI2 pin status
Read FGPI1 pin status
Read FGPI0 pin status
FUNCTION
-5-
Publication Release Date: December 19, 2002
Revision A2
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