W77C32/W77C032A
Table 6. SFR Reset Value
SFR NAME
P0
SP
DPL
DPH
DPL1
DPH1
DPS
PCON
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
P1
SCON
SBUF
P2
SADDR1
SCON1
ROMMAP
EXIF
P4
RESET VALUE
11111111b
00000111b
00000000b
00000000b
00000000b
00000000b
00000000b
00xx0000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000000b
00000001b
11111111b
00000000b
SFR NAME
IE
SADDR
P3
IP
SADEN
T2CON
T2MOD
RCAP2L
RCAP2H
TL2
TH2
TA
PSW
WDCON
ACC
EIE
B
EIP
PC
SADEN1
SBUF1
PMR
STATUS
RESET VALUE
00000000b
00000000b
11111111b
x0000000b
00000000b
00000000b
00000x00b
00000000b
00000000b
00000000b
00000000b
11111111b
00000000b
0x0x0xx0b
00000000b
xxx
00000b
00000000b
xxx00000b
00000000b
00000000b
xxxxxxxx
b
11111111b
00000000b
00000000b
01
xxxxxx
b
0000
xxx
0b
xxxxxxxx
b
010xx0x0b
000x0000b
xxxx
1111b
The WDCON SFR bits are set/cleared in reset condition depending on the source of the reset.
External reset
WDCON
0x0x0xx0b
Watchdog reset Power on reset
0x0x01x0b
01000000b
The POR bit WDCON.6 is set only by the power on reset. The WTRF bit WDCON.2 is set when the
Watchdog timer causes a reset. A power on reset will also clear this bit. The EWT bit WDCON.1 is
cleared by power on resets. This disables the Watchdog timer resets. A watchdog or external reset
does not affect the EWT bit.
- 46 -
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