W77E058A
4. PIN DESCRIPTION
SYMBOL TYPE
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM
I
EA
address and data will not be present on the bus if EA pin is high and the
program counter is within 32 KB area. Otherwise they will be present on the
bus.
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the
O
Port 0 address/data bus during fetch and MOVC operations. When internal
PSEN
ROM access is performed, no PSEN strobe signal outputs from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
ALE
RST
O
I
separates the address from the data on Port 0.
RESET: A high on this pin for two machine cycles while the oscillator is running
resets the device.
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an
XTAL1
I
external clock.
XTAL2
VSS
O
I
CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: Ground potential
VDD
I
POWER SUPPLY: Supply voltage for operation.
PORT 0: Port 0 is an open-drain bi-directional I/O port. This port also provides a
I/O
I/O
I/O
P0.0−P0.7
P1.0−P1.7
P2.0−P2.7
multiplexed low order address/data bus during accesses to external memory.
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have
alternate functions which are described below:
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture/Direction control
RXD1(P1.2): Serial port 1 RXD
TXD1(P1.3): Serial port 1 TXD
INT2(P1.4): External Interrupt 2
INT3 (P1.5): External Interrupt 3
INT4(P1.6): External Interrupt 4
INT5 (P1.7): External Interrupt 5
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory.
Publication Release Date: April 17, 2007
- 5 -
Revision A10
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