W77IE58/W77I058A
Timers
The W77I058 has three 16-bit timers that are functionally similar to the timers of the 8052 family.
When used as timers, they can be set to run at either 4 clocks or 12 clocks per count, thus providing
the user with the option of operating in a mode that emulates the timing of the original 8052. The
W77I058 has an additional feature, the watchdog timer. This timer is used as a System Monitor or as
a very long time period timer.
Interrupts
The Interrupt structure in the W77I058 is slightly different from that of the standard 8052. Due to the
presence of additional features and peripherals, the number of interrupt sources and vectors has been
increased. The W77I058 provides 12 interrupt resources with two priority level, including six external
interrupt sources, timer interrupts, serial I/O interrupts.
Data Pointers
The original 8052 had only one 16-bit Data Pointer (DPL, DPH). In the W77I058, there is an additional
16-bit Data Pointer (DPL1, DPH1). This new Data Pointer uses two SFR locations which were unused
in the original 8052. In addition there is an added instruction, DEC DPTR (op-code A5H), which helps
in improving programming flexibility for the user.
Power Management
Like the standard 80C52, the W77I058 also has IDLE and POWER DOWN modes of operation. The
W77I058 provides a new Economy mode which allow user to switch the internal clock rate divided by
either 4, 64 or 1024. In the IDLE mode, the clock to the CPU core is stopped while the timers, serial
ports and interrupts clock continue to operate. In the POWER DOWN mode, all the clock are stopped
and the chip operation is completely stopped. This is the lowest power consumption state.
On-chip Data SRAM
The W77I058 has 1K Bytes of data space SRAM which is read/write accessible and is memory
mapped. This on-chip MOVX SRAM is reached by the MOVX instruction. It is not used for executable
program memory. There is no conflict or overlap among the 256 bytes Scratchpad RAM and the 1K
Bytes MOVX SRAM as they use different addressing modes and separate instructions. The on-chip
MOVX SRAM is enabled by setting the DME0 bit in the PMR register. After a reset, the DME0 bit is
cleared such that the on-chip MOVX SRAM is disabled, and all data memory spaces 0000H−FFFFH
access to the external memory.
-7-
Publication Release Date: November 10, 2006
Revision A7
WINBOND [ WINBOND ]
