W78C32C
Program Fetch Cycle
PARAMETER
Address Valid to ALE Low
Address Hold after ALE Low
ALE Low to
PSEN
Low
PSEN Low to Data Valid
Data Hold after PSEN High
Data Float after PSEN High
ALE Pulse Width
SYMBOL
T
AAS
T
AAH
T
APL
T
PDA
T
PDH
T
PDZ
T
ALW
T
PSW
MIN.
1 T
CP
-∆
1 T
CP
-∆
1 T
CP
-∆
-
0
0
2 T
CP
-∆
3 T
CP
-∆
TYP.
-
-
-
-
-
-
2 T
CP
3 T
CP
MAX.
-
-
-
2 T
CP
1 T
CP
1 T
CP
-
-
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
4
4
NOTES
4
1, 4
4
2
3
PSEN
Pulse Width
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 T
CP
.
3. Data have been latched internally prior to PSEN going high.
4. "∆" ( due to buffer driving delay and wire loading) is 20 nS.
Data Read Cycle
PARAMETER
ALE Low to
RD
Low
RD
Low to Data Valid
SYMBOL
T
DAR
T
DDA
T
DDH
T
DDZ
T
DRD
MIN.
3 T
CP
-∆
-
0
0
6 T
CP
-∆
TYP.
-
-
-
-
6 T
CP
MAX.
3 T
CP+
∆
4 T
CP
2 T
CP
2 T
CP
-
UNIT
nS
nS
nS
nS
nS
NOTE
S
1, 2
1
Data Hold after
RD
High
Data Float after RD High
RD Pulse Width
2
Notes:
1. Data memory access time is 8 T
CP
.
2. "∆" (due to buffer driving delay and wire loading) is 20 nS.
Data Write Cycle
PARAMETER
ALE Low to WR Low
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
SYMBOL
T
DAW
T
DAD
T
DWD
T
DWR
MIN.
3 T
CP
-∆
1 T
CP
-∆
1 T
CP
-∆
6 T
CP
-∆
TYP.
-
-
-
6 T
CP
MAX.
3 T
CP+
∆
-
-
-
UNIT
nS
nS
nS
nS
Note: "∆" ( due to buffer driving delay and wire loading) is 20 nS.
-8-
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