W79E804A/803A/802A
CLOCK CONTROL
Bit:
7
-
6
-
5
-
4
3
2
-
1
-
0
-
T1M
T0M
Mnemonic: CKCON
Address: 8Eh
BIT NAME
FUNCTION
7-5
-
Reserved.
Timer 1 clock select:
4
T1M
0: Timer 1 uses a divide by 12 clocks.
1: Timer 1 uses a divide by 4 clocks.
Timer 0 clock select:
3
T0M
-
0: Timer 0 uses a divide by 12 clocks.
1: Timer 0 uses a divide by 4 clocks.
2-0
Reserved.
PORT 1
Bit:
7
6
5
4
3
2
1
0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
Mnemonic: P1
Address: 90h
P1.7-0: General purpose Input/Output port. Most instructions will read the port pins in case of a port
read access, however in case of read-modify-write instructions, the port latch is read. These alternate
functions are described below:
BIT
NAME
FUNCTION
7
6
5
4
3
2
1
0
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1
P1.0
PWM 2 Pin.
PWM 1 Pin.
/RST Pin or Input Pin by alternative.
/INT1 interrupt.
/INT0 interrupt or SDA of I2C.
Timer 0 or SCL of I2C.
RXD of Serial port.
TXD of Serial port.
Note: The initial value of the port is set by CONFIG1.PRHI bit. The default setting for CONFIG1.PRHI =1 which the alternative
function output is turned on upon reset. If CONFIG1.PRHI is set to 0, the user has to write a 1 to port SFR to turn on the
alternative function output.
DIVIDER CLOCK
Bit:
7
6
5
4
3
2
1
0
DIVM.7
DIVM.6
DIVM.5
DIVM.4
DIVM.3
DIVM.2
DIVM.1
DIVM.0
Mnemonic: DIVM
BIT NAME
Address: 95h
FUNCTION
7-0 DIVM.[7:0] The DIVM register is clock divider of uC. Refer OSCILLATOR chapter.
Publication Release Date: July 16, 2007
Revision A2
- 23 -
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