W79E804A/803A/802A
9. INSTRUCTION SET
The W79E804 series execute all the instructions of the standard 8052 family. The operations of these
instructions, as well as their effects on flag and status bits, are exactly the same. However, the timing
of these instructions is different in two ways. Firstly, the machine cycle is four clock periods, while the
standard-8051/52 machine cycle is twelve clock periods. Secondly, it can fetch only once per machine
cycle (i.e., four clocks per fetch), while the standard 8051/52 can fetch twice per machine cycle (i.e.,
six clocks per fetch).
The timing differences create an advantage for the W79E804 series. There is only one fetch per
machine cycle, so the number of machine cycles is usually equal to the number of operands in the
instruction. (Jumps and calls do require an additional cycle to calculate the new address.) As a result,
the W79E804 series reduces the number of dummy fetches and wasted cycles, and therefore
improves overall efficiency, compared to the standard 8051/52.
W79E804
SERIES
MACHINE
CYCLE
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
OP-CODE
HEX CODE BYTES
W79E804
SERIES
CLOCK
CYCLES
4
4
4
4
4
4
4
4
4
4
4
8
8
4
4
4
4
4
4
4
4
4
8032
CLOCK
CYCLES
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
W79E804
SERIES VS.
8032 SPEED
RATIO
3
3
3
3
3
3
3
3
3
3
3
1.5
1.5
3
3
3
3
3
3
3
3
3
NOP
ADD A, R0
ADD A, R1
ADD A, R2
ADD A, R3
ADD A, R4
ADD A, R5
ADD A, R6
ADD A, R7
ADD A, @R0
ADD A, @R1
ADD A, direct
ADD A, #data
ADDC A, R0
ADDC A, R1
ADDC A, R2
ADDC A, R3
ADDC A, R4
ADDC A, R5
ADDC A, R6
ADDC A, R7
ADDC A, @R0
00
28
29
2A
2B
2C
2D
2E
2F
26
27
25
24
38
39
3A
3B
3C
3D
3E
3F
36
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
- 45 -
Publication Release Date: July 16, 2007
Revision A2
WINBOND [ WINBOND ]
