W83194R-630/-630A Data Sheet
166MHZ CLOCK FOR SIS CHIPSET
Table of Content-
1.
2.
3.
4.
5.
GENERAL DESCRIPTION ......................................................................................................... 2
PRODUCT FEATURES .............................................................................................................. 2
BLOCK DIAGRAM ...................................................................................................................... 3
PIN CONFIGURATION ............................................................................................................... 4
PIN DESCRIPTION..................................................................................................................... 4
5.1
5.2
5.3
5.4
5.5
6.
7.
8.
Crystal I/O ....................................................................................................................... 4
CPU, SDRAM, PCI Clock Outputs ................................................................................ 5
I
2
C Control Interface ....................................................................................................... 6
Fixed Frequency Outputs ............................................................................................... 6
Power Pins...................................................................................................................... 6
FREQUENCY SELECTION BY HARDWARE ............................................................................ 7
SEL3.3_2.5# BUFFER SELECTION ......................................................................................... 7
FUNCTION DESCRIPTION........................................................................................................ 8
8.1
8.2
2-WIRE I2C CONTROL INTERFACE ............................................................................ 8
SERIAL CONTROL REGISTERS .................................................................................. 9
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.2.7
8.2.8
Frequency table by I2C ....................................................................................................9
Register 0: CPU Frequency Select Register (default = 0) .............................................10
Register 1 : CPU Clock Register (1 = Active, 0 = Inactive).............................................10
Register 2: PCI Clock Register (1 = Active, 0 = Inactive) ..............................................11
Register 3: Control Register (1 = Active, 0 = Inactive)...................................................11
Register 4: SDRAM Register (1 = Active, 0 = Inactive) ..................................................11
Register 5: SDRAM Register(1 = Active, 0 = Inactive) ...................................................12
Register 6: Winbond Chip ID Register (Read Only)......................................................12
9.
10.
11.
12.
ORDERING INFORMATION .................................................................................................... 12
HOW TO READ THE TOP MARKING...................................................................................... 13
PACKAGE DRAWING AND DIMENSIONS.............................................................................. 14
REVISION HISTORY ................................................................................................................ 15
-1-
Publication Release Date: May 13, 2005
Revision A1
WINBOND [ WINBOND ]
