W83627DHG
10.1.2 Data Separator
The function of the data separator is to lock onto incoming serial read data. When a lock is achieved,
the serial front-end logic in the chip is provided with a clock that is synchronized with the read data. The
synchronized clock, called the Data Window, is used to internally sample the serial data portion of the
bit cell, and the alternate state samples the clock portion. Serial-to-parallel conversion logic separates
the read data into clock and data bytes.
The Digital Data Separator (DDS) has three parts: control logic, error adjustment, and speed tracking.
The control logic generates RDD and RWD for every pulse input, and any data pulse input is
synchronized and then adjusted immediately by error adjustment. A digital integrator keeps track of the
speed changes in the input data stream.
10.1.3 Write Precompensation
The write precompensation logic minimizes bit shifts in the RDDATA stream from the disk drive.
Shifting of bits is a known phenomenon in magnetic media and depends on the disk media and the
floppy drive.
The FDC monitors the bit stream that is being sent to the drive. The data patterns that require
precompensation are well known, so, depending on the pattern, the bit is shifted either early or late,
relative to the surrounding bits.
10.1.4 Perpendicular Recording Mode
The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular
recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically.
This scheme packs more data bits into the same area.
FDCs with perpendicular recording drives can read standard 3.5" floppy disks and can read and write
perpendicular media. Some manufacturers offer drives that can read and write standard and
perpendicular media in a perpendicular media drive.
A single command puts the FDC into perpendicular mode. All other commands operate as they
normally do. Perpendicular mode requires a 1 Mbps data rate for the FDC, and, at this data rate, the
FIFO manages the host interface bottleneck due to the high speed of data transfer to and from the disk.
10.1.5 FDC Core
The W83627DHG FDC is capable of performing twenty commands. Each command is initiated by a
multi-byte transfer from the microprocessor, and the result may be a multi-byte transfer back to the
microprocessor. Each command consists of three phases: command, execution, and result.
Command
The microprocessor issues all required information to the controller to perform a specific operation.
Execution
The controller performs the specified operation.
Result
After the operation is completed, status information and other housekeeping information are provided
to the microprocessor.
The next section introduces each of the commands.
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Publication Release Date: Aug, 22, 2007
Version 1.4
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