W986408CH
2M x 8 bit x 4 Banks SDRAM
NOTES:
1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.
2. All voltages are referenced to V
SS
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of
tCK and t
RC
.
4. These parameters depend on the output loading conditions. Specified values are obtained with output open.
5. Power up sequence is further described in the "Functional Description" section.
6. AC TESTING CONDITIONS
Output Reference Level
Output Load
Input Signal Levels
Transition Time (Rise and Fall) of Input Signal
Input Reference Level
3.3 V
1.4V/1.4V
See diagram B below
2.4V/0.4V
2ns
1.4V
1.4 V
1.2K
50 ohms
output
50pF
0.87K
output
Z = 50 ohms
50pF
AC TEST LOAD (A)
7. Transition times are measured between V
IH
and V
IL
.
AC TEST LOAD (B)
8. t
HZ
defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.
Revision 1.0
-8-
Publication Release Date: March, 1999
WINBOND [ WINBOND ]
