WM8141
INPUT VIDEO SAMPLING
t
PER
MCLK
t
VSMPSU
VSMP
INPUT
t
VSU
VIDEO
t
VH
t
RSU
t
RH
t
VSMPH
t
MCLKH
t
MCLKL
Production Data
Figure 1 Input Video Timing
Test Conditions
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, T
A
= 0 to 70°C, MCLK = 12MHz unless otherwise stated
PARAMETER
MCLK period
MCLK high period
MCLK low period
VSMP set-up time
VSMP hold time
Video level set-up time
Video level hold time
Reset level set-up time
Reset level hold time
Notes:
1.
2.
SYMBOL
t
PER
t
MCLKH
t
MCLKL
t
VSMPSU
t
VSMPH
t
VSU
t
VH
t
RSU
t
RH
TEST CONDITIONS
MIN
83.3
37.5
37.5
10
10
10
15
10
15
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
VSU
and t
RSU
denote the set-up time required after the input video signal has settled.
Parameters are measured at 50% of the rising/falling edge.
OUTPUT DATA TIMING
MCLK
t
PD
OP[11:0]
Figure 2 Output Data Timing
WOLFSON MICROELECTRONICS LTD
PD Rev 3.0 October 2000
8
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
