WM8150
Production Data
REFERENCES
The ADC reference voltages are derived from an internal bandgap reference, and buffered to pins
VRT and VRB, where they must be decoupled to ground. Pin VRX is driven by a similar buffer, and
also requires decoupling. The output buffer from the RLCDAC also requires decoupling at pin
VRLC/VBIAS when this is configured as an output.
POWER SUPPLY
The WM8150 can run from a 5V single supply or from split 5V (core) and 3.3V (digital interface)
supplies.
POWER MANAGEMENT
Power management for the device is performed via the Control Interface. The device can be powered
on or off completely by setting the EN bit low.
All the internal registers maintain their previously programmed value in power down mode and the
Control Interface inputs remain active.
OPERATING MODES
Table 3 summarises the most commonly used modes, the clock waveforms required and the register
contents required for CDS and non-CDS operation.
MODE
DESCRIPTION
CDS
AVAILABLE
MAX
SAMPLE
RATE
TIMING
REQUIREMENTS
REGISTER
CONTENTS WITH
CDS
REGISTER
CONTENTS
WITHOUT CDS
1
Monochrome/
Colour Line-by-Line
Yes
Yes
2.67MSPS MCLK max = 16MHz SetReg1: 0F(hex)
SetReg1: 0D(hex)
MCLK:VSMP ratio is
6:1
2
Fast Monochrome/
Colour Line-by-Line
5.33MSPS MCLK max = 16MHz Identical to Mode
Identical to
Mode 1
1 plus SetReg3:
bits 5:4 must be
set to 0(hex)
MCLK:VSMP ratio is
3:1
3
4
Maximum speed
Monochrome/
Colour Line-by-Line
No
8MSPS
2MSPS
MCLK max = 16MHz CDS not possible
SetReg1: 4D(hex)
MCLK:VSMP ratio is
2:1
Slow Monochrome/
Colour Line-by-Line
Yes
MCLK max = 16MHz Identical to
Identical to
Mode 1
Mode 1
MCLK:VSMP ratio is
2n:1, n ≥ 4
Table 3 WM8150 Operating Modes
PD Rev 3.0 November 2002
16
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
