WM8196
Production Data
MCLK
VSMP
VS
RS/CL (CDSREF = 00)
RS/CL (CDSREF = 01)
RS/CL (CDSREF = 10)
RS/CL (CDSREF = 11)
Figure 11 Reset Sample and Clamp Timing
For CIS type sensor signals, non-CDS processing is used. In this case, the video level is processed
with respect to the voltage on pin VRLC/VBIAS, generated internally or externally as described
above. The VRLC/VBIAS pin is sampled by Rs at the same time as Vs samples the video level in this
mode; non-CDS processing is achieved by setting switch 2 in the lower position, CDS = 0.
OFFSET ADJUST AND PROGRAMMABLE GAIN
The output from the CDS block is a differential signal, which is added to the output of an 8-bit Offset
DAC to compensate for offsets and then amplified by an 8-bit PGA. The gain and offset for each
channel are independently programmable by writing to control bits DAC[7:0] and PGA[7:0].
The gain characteristic of the WM8196 PGA is shown in Figure 12. Figure 13 shows the maximum
device input voltage that can be gained up to match the ADC full-scale input range (3V).
8
7
6
5
4
3
2
1
0
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
64
128
192
256
0
64
128
192
256
Gain register value (PGA[7:0])
Gain register value (PGA[7:0])
Figure 12 PGA Gain Characteristic
Figure 13 Peak Input Voltage to Match ADC Full-scale Range
In colour line-by-line mode the gain and offset coefficients for each colour can be multiplexed in order
(Red → Green → Blue → Red…) by pulsing the ACYC/RLC pin, or controlled via the FME,
ACYCNRLC and INTM[1:0] bits. Refer to the Line-by-Line Operation section for more details.
PD Rev 4.3 March 2007
15
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WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
