WM8521
MASTER CLOCK TIMING
t
MCLKL
MCLK
t
MCLKH
t
MCLKY
Product Preview
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK Master clock pulse width
high
MCLK Master clock pulse width
low
MCLK Master clock cycle time
MCLK Duty cycle
Time from MCLK stopping to
digital reset
t
MCLKH
t
MCLKL
t
MCLKY
11
11
28
40:60
1.5
60:40
12
µs
ns
ns
ns
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL AUDIO INTERFACE
t
BCH
t
BCL
BCLK
t
BCY
LRCLK
t
DS
t
LRH
t
LRSU
DIN
t
DH
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD = 12V, DVDD = 3.3V, AGND / DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK
rising edge
LRCLK hold time from
BCLK rising edge
DIN set-up time to BCLK
rising edge
DIN hold time from BCLK
rising edge
SYMBOL
t
BCY
t
BCH
t
BCL
t
LRSU
t
LRH
t
DS
t
DH
TEST CONDITIONS
MIN
50
20
20
10
10
10
10
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
Audio Data Input Timing Information
w
PP Rev 1.3 December 2004
8
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
