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WM8591
MASTER CLOCK TIMING
t
MCLKL
MCLK
t
MCLKH
t
MCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, ADC/DACMCLK = 256fs unless otherwise
stated.
PARAMETER
System Clock Timing Information
ADC/DACMCLK System clock
pulse width high
ADC/DACMCLK System clock
pulse width low
ADC/DACMCLK System clock
cycle time
ADC/DACMCLK Duty cycle
Table 1 Master Clock Timing Requirements
t
MCLKH
t
MCLKL
t
MCLKY
11
11
27
40:60
60:40
ns
ns
ns
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL AUDIO INTERFACE – MASTER MODE
DACBCLK
ADCBCLK
ADCLRC
WM8591
CODEC DACLRC
DOUT
DIN
DVD
Controller
Figure 2 Audio Interface – Master Mode
w
PP Rev 1.0 May 2005
9
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
