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WM8602
CONTROL INTERFACE TIMING – 3-WIRE MODE
t
CSL
CSB
t
SCY
t
SCH
SCLK
t
SCL
t
SCS
t
CSH
t
CSS
SDIN
t
DSU
t
DHO
LSB
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data,
unless otherwise stated.
PARAMETER
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes that will be suppressed
Table 6 Control Interface Timing – 3-Wire Serial Control Mode
t
SCS
t
SCY
t
SCL
t
SCH
t
DSU
t
DHO
t
CSL
t
CSH
t
CSS
t
ps
60
80
30
30
20
20
20
20
20
2
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
MIN
TYP
MAX
UNIT
w
PP Rev 1.5 May 2004
11
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
