Production Data
WM8716
t
SCKIL
SCKI
t
SCKIH
Figure 2 System Clock Timing Requirements
TEST CONDITIONS
AVDD, DVDD = 5V, AGND, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
System Clock Timing Information
SCKI System clock pulse width high
SCKI System clock pulse width low
t
SCKIH
t
SCKIL
13
13
ns
ns
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
MLL
ML/I2S (PIN 28)
t
MCY
t
MCH
t
MCL
t
MHH
t
MLH
t
MLS
MC/DM1 (PIN 27)
t
MDS
MD/DM0 (PIN 26)
t
CSML
CSBIWO (PIN 23)
t
MDH
LSB
t
MLCS
Figure 3 Program Register Input Timing
TEST CONDITIONS
AVDD, DVDD = 5V, AGND, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, SCKI = 256fs unless otherwise stated.
PARAMETER
Program Register Input Information
MC/DM1 Pulse cycle time
MC/DM1 Pulse width LOW
MC/DM1 Pulse width HIGH
MD/DM0 Hold time
MD/DM0 Set-up time
ML/I2S Low level time
(See Note 3)
ML/I2S High level time
(See Note 3)
ML/I2S Hold time
ML/I2S Set-up time
CSBIWO Low to ML/I2S low time
ML/I2S High to CSBIWO high time
Note:
3.
System clock cycle.
t
MCY
t
MCL
t
MCH
t
MDH
t
MDS
t
MLL
t
MHH
t
MLH
t
MLS
t
CSML
t
MLCS
100
40
40
40
40
40 +
1SYSCLK
40 +
1SYSCLK
40
40
10
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
w
PD, Rev 4.2, August 2008
7
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
