WM8716
AUDIO DATA INTERFACE
Production Data
Data may be input at a rate corresponding to the system clock having a rate of 256fs or 384fs or
512fs or 768fs, in which case an oversampling ratio of 128x is selected. Alternatively a rate of 128fs
or 192fs may be used, in which case the first filter stage is bypassed and an oversampling ratio of
64x results. Finally, in MODE8X, data may be input at 8x the normal rate, in which case separate
input pins are used to input the two stereo channels of data (unless DIFFHW mode and MODE8X
are both selected, in which case only a mono channel is converted differentially). In MODE8X all filter
stages are by-passed, prior to the sigma delta modulator. Data is input MSB first in all modes.
NORMAL SAMPLE RATE
In normal mode, the data is input serially on one pin for both left and right channels.
Data can be “right justified” meaning that the last 16, 20 or 24 bits (depending on chosen PCM word
length) that were clocked in prior to the transition on LRCIN are valid.
Alternatively data can be “left justified” (20 and 24-bit PCM data only), where the bits are clocked in
as the first 20 or 24 bits after a transition on LRCIN.
For the three I
2
S modes supported (16-bit, 20-bit and 24-bit PCM data), data is clocked “left justified”
except with one additional preceding clock cycle.
1/fs
LEFT
LRCIN (PIN 1)
RIGHT
BCKIN (PIN 3)
16-BIT RIGHT
JUSTIFIED
DIN (PIN 2)
20-BIT RIGHT
JUSTIFIED
DIN (PIN 2)
24-BIT RIGHT
JUSTIFIED
DIN (PIN 2)
24-BIT LEFT
JUSTIFIED
DIN (PIN 2)
20-BIT LEFT
JUSTIFIED
DIN (PIN 2)
B2 B1 B0
B15
B2
B1
B0
B15
B2
B1 B0
B2
B1
B0
B19 B18 B17
B2
B1
B0
B19 B18 B17
B2
B1 B0
B2 B1
B0
B23 B22 B21 B20 B19
B2
B1
B0
B23 B22 B21 B20 B19
B2
B1 B0
B0
B23 B22 B21
B4
B3
B2 B1
B0
B23 B22 B21
B4
B3
B2 B1
B0
B0
B19 B18 B17
B0
B19 B18 B17
B0
LEFT
LRCIN (PIN 1)
RIGHT
BCKIN (PIN 3)
16-BIT I
2
S
DIN (PIN 2)
B15
B2
B1 B0
B15
B2
B1 B0
B15
24-BIT I
2
S
DIN (PIN 2)
B23
B6
B5 B4 B3
B2 B1
B0
B23
B6
B5 B4 B3
B2 B1 B0
B23
20-BIT I
2
S
DIN (PIN 2)
B19
B2
B1 B0
B19
B2
B1 B0
B19
Figure 4 Audio Data Input Format
w
PD Rev 4.1 September 2006
10