WM8738
DIGITAL AUDIO INTERFACE TIMING
t
MCLKL
M CLK
t
MCLKH
t
MCLKY
Production Data
Figure 1 Master Clock Timing Requirements
Test Conditions
AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
SYMBOL
T
MCLKH
T
MCLKL
T
MCLKY
TEST CONDITIONS
MIN
10
10
27
TYP
MAX
UNIT
ns
ns
ns
t
BCH
BCLK
t
BCY
t
BCL
LRCLK
t
DD
SDATO
t
LRH
t
LRS U
Figure 2 Digital Audio Data Timing
Test Conditions
AVDD = 5.0V, AGND = 0V, DVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
LRCLK set-up time to BCLK
rising edge
LRCLK hold time from
BCLK rising edge
SDATO propagation delay
from BCLK falling edge
SYMBOL
t
BCY
t
BCH
t
BCL
t
LRSU
t
LRH
t
DD
TEST CONDITIONS
MIN
TYP
80
40
40
10
10
10
MAX
UNIT
ns
ns
ns
ns
ns
ns
Audio Data Input Timing Information
w
PD Rev 4.3 November 2004
8
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
