WM8739 / WM8739L
DIGITAL AUDIO INTERFACE TIMING
t
XTIL
XTI/MCLK
t
XTIH
t
XTIY
Advanced Information
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, Slave Mode fs = 48kHz, XTI/MCLK = 256fs
unless otherwise stated.
PARAMETER
System Clock Timing Information
XTI/MCLK System clock pulse width
high
XTI/MCLK System clock pulse width
low
XTI/MCLK System clock cycle time
SYMBOL
T
XTIH
T
XTIL
T
XTIY
TEST CONDITIONS
MIN
20
20
50
TYP
MAX
UNIT
ns
ns
ns
BCLK
DSP
ENCODER
WM8739
ADCLRC
ADC
ADCDAT
Figure 2 Master Mode Connection
BCLK
(Output)
t
DL
ADCLRC
(Output)
t
DDA
ADCDAT
Figure 3 Digital Audio Data Timing – Master Mode
AI Rev 2.2 September 2001
7
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
