WM8759
MASTER CLOCK TIMING
t
MCLKL
MCLK
t
MCLKH
t
MCLKY
Advanced Information
Figure 1 Master Clock Timing Requirements
Test Conditions
VDD = 5V, GND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK Master clock pulse width high
MCLK Master clock pulse width low
MCLK Master clock cycle time
MCLK Duty cycle
Time from MCLK stopping to power
down.
SYMBOL
t
MCLKH
t
MCLKL
t
MCLKY
TEST CONDITIONS
MIN
8
8
20
40:60
1.5
TYP
MAX
UNIT
ns
ns
ns
60:40
12
µs
DIGITAL AUDIO INTERFACE
t
BCH
BCKIN
t
BCY
t
BCL
LRCIN
t
DS
DIN
t
DH
t
LRH
t
LRSU
Figure 2 Digital Audio Data Timing
Test Conditions
VDD = 5V, GND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
BCKIN cycle time
BCKIN pulse width high
BCKIN pulse width low
LRCIN set-up time to
BCKIN rising edge
LRCIN hold time from
BCKIN rising edge
DIN set-up time to BCKIN
rising edge
DIN hold time from BCKIN
rising edge
SYMBOL
t
BCY
t
BCH
t
BCL
t
LRSU
t
LRH
t
DS
t
DH
TEST CONDITIONS
MIN
40
16
16
8
8
8
8
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
Audio Data Input Timing Information
w
AI Rev 3.0 September 2004
8
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
