WM8762
MASTER CLOCK TIMING
t
MCLKL
MCLK
t
MCLKH
t
MCLKY
Production Data
Figure 4 Master Clock Timing Requirements
Test Conditions
VDD = 5V, GND = 0V, T
A
= +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK Master clock pulse width high
MCLK Master clock pulse width low
MCLK Master clock cycle time
MCLK Duty cycle
Time from MCLK stopping to power
down.
t
MCLKH
t
MCLKL
t
MCLKY
8
8
20
40:60
1.5
60:40
12
s
ns
ns
ns
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
o
DIGITAL AUDIO INTERFACE
t
BCH
BCKIN
t
BCY
t
BCL
LRCIN
t
DS
DIN
t
DH
t
LRH
t
LRSU
Figure 5 Digital Audio Data Timing
Test Conditions
VDD = 5V, GND = 0V, T
A
= +25 C, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
BCKIN cycle time
BCKIN pulse width high
BCKIN pulse width low
LRCIN set-up time to BCKIN rising
edge
LRCIN hold time from BCKIN rising
edge
DIN set-up time to BCKIN rising edge
DIN hold time from BCKIN rising edge
t
BCY
t
BCH
t
BCL
t
LRSU
t
LRH
t
DS
t
DH
40
16
16
8
8
8
8
ns
ns
ns
ns
ns
ns
ns
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
o
w
PD, Rev 4.6, November 2011
8
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
