WM8955BL
PIN DESCRIPTION
PIN NO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
MCLK
DCVDD
DBVDD
DGND
BCLK
DACDAT
DACLRC
PLLGND
MONOOUT
OUT3
ROUT1
LOUT1
HPGND
ROUT2
LOUT2
HPVDD
AVDD
AGND
VREF
VMID
MONOIN-
MONOIN+
LINEINR
LINEINL
MODE
CSB
SDIN
SCLK
TYPE
Digital Input
Supply
Supply
Supply
Digital Input / Output
Digital Input
Digital Input / Output
Supply
Analogue Output
Analogue Output
Analogue Output
Analogue Output
Supply
Analogue Output
Analogue Output
Supply
Supply
Supply
Analogue Output
Analogue Output
Analogue Input
Analogue Input
Analogue Input
Analogue Input
Digital Input
Digital Input
Digital Input/Output
Digital Input
Master Clock
Digital Core Supply
Digital Buffer (I/O) Supply
DESCRIPTION
Production Data
Digital Ground (return path for both DCVDD and DBVDD)
Audio Interface Bit Clock
DAC Digital Audio Data
Audio Interface Left / Right Clock
Internally connected to AGND. Connect this pin to AGND externally
for best PLL performance, or leave floating.
Mono Output
Output 3 (can be used as Headphone Pseudo Ground)
Right Output 1 (Line or Headphone)
Left Output 1 (Line or Headphone)
Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2)
Right Output 2 (Line or Headphone or Earpiece)
Left Output 2 (Line or Headphone or Earpiece)
Supply for Analogue Output Drivers (LOUT1/2, ROUT1/2, MONOUT)
Analogue Supply
Analogue Ground (return path for AVDD)
Reference Voltage Decoupling Capacitor
Midrail Voltage Decoupling Capacitor
Negative end of MONOIN+, for differential mono signals
Analogue Line-in to mixers (mono channel)
Analogue Line-in to mixers (right channel)
Analogue Line-in to mixers (left channel)
Control Interface Selection
Chip Select / Device Address Selection
Control Interface Data Input / 2-wire Acknowledge output
Control Interface Clock Input
w
PD Rev 4.1 February 2007
4