Product Preview
WM8955L
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
t
MCLKL
MCLK
t
MCLKH
t
MCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
DBVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
SYMBOL
t
MCLKL
t
MCLKH
t
MCLKY
MIN
16
16
27
TYP
MAX
UNIT
ns
ns
ns
AUDIO INTERFACE TIMING – MASTER MODE
BCLK
(Output)
t
DL
DACLRC
(Output)
t
DST
DACDAT
t
DHT
Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)
Test Conditions
DBVDD = 3.3V, DGND = 0V, T
A
= +25
o
C, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated.
PARAMETER
System Clock Timing Information
DACLRC propagation delay from BCLK falling edge
DACDAT setup time to BCLK rising edge
DACDAT hold time from BCLK rising edge
SYMBOL
t
DL
t
DST
t
DHT
MIN
TYP
MAX
10
UNIT
ns
ns
ns
10
10
AUDIO INTERFACE TIMING – SLAVE MODE
t
BCH
BCLK
t
BCY
t
BCL
DACLRC
t
DS
DACDAT
t
LRH
t
LRSU
Figure 3 Digital Audio Data Timing – Slave Mode (see Control Interface)
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Product Preview Rev 0.4 May 2003
11
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
