WM9705
Production Data
WARM RESET
tSYNC_HIGH
tSYNC2CLK
SYNC
BITCLK
Figure 6 Warm Reset Timing
PARAMETER
SYMBOL
tSYNC_HIGH
tSYNC2CLK
MIN
TYP
MAX
UNIT
µs
SYNC active high pulse width
1.3
SYNC inactive to BITCLK startup
delay
162.4
ns
CLOCK SPECIFICATIONS
tCLK_HIGH
tCLK_LOW
BITCLK
tCLK_PERIOD
tSYNC_HIGH
tSYNC_LOW
SYNC
tSYNC_PERIOD
Figure 7 Clock Specifications (50pF External Load)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
MHz
ns
BITCLK frequency
BITCLK period
12.288
81.4
tCLK_PERIOD
BITCLK output jitter
BITCLK high pulse width (Note 1)
BITCLK low pulse width (Note 1)
SYNC frequency
750
45
ps
tCLK_HIGH
tCLK_LOW
36
36
40.7
40.7
48.0
20.8
1.3
ns
45
ns
kHz
µs
SYNC period
tSYNC_PERIOD
tSYNC_HIGH
tSYNC_LOW
SYNC high pulse width
SYNC low pulse width
Note:
µs
19.5
µs
Worst case duty cycle restricted to 45/55.
PD Rev 4.0 December 2003
14
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
