WM9707
WARM RESET
t
SYNC_HIGH
SYNC
t
SYNC2CLK
Advanced Information
BIT_CLK
Figure 3 Warm Reset Timing
PARAMETER
SYNC active high pulse width
SYNC inactive to BIT_CLK startup
delay
SYMBOL
t
SYNC_HIGH
t
SYNC2_CLK
162.4
MIN
TYP
1.3
MAX
UNIT
µs
ns
CLOCK SPECIFICATIONS
t
CLK_HIGH
BIT_CLK
t
CLK_PERIOD
t
SYNC_HIGH
SYNC
t
SYNC_PERIOD
t
SYNC_LOW
t
CLK_LOW
Figure 4 Clock Specifications (50pF External Load)
Note: Worst case duty cycle restricted to 40/60.
PARAMETER
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter
BIT_CLK high pulse width
( See Note)
BIT_CLK low pulse width
( See Note)
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
t
SYNC_PERIOD
t
SYNC_HIGH
t
SYNC_LOW
t
CLK_HIGH
t
CLK_LOW
32.56
32.56
40.7
40.7
48.0
20.8
1.3
19.5
t
CLK_PERIOD
SYMBOL
MIN
TYP
12.288
81.4
750
48.84
48.84
MAX
UNIT
MHz
ns
ps
ns
ns
kHz
µs
µs
µs
WOLFSON MICROELECTRONICS LTD
AI Rev 2.2 January 2001
8
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
