X24C01A
Sequential Read
Sequential Read can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating it
requires additional data. The X24C01A continues to
output data for each acknowledge received. The read
operation is terminated by the master, by not responding
with an acknowledge and by issuing a stop condition.
Figure 9. Sequential Read
SLAVE
BUS ACTIVITY:
ADDRESS
MASTER
SDA LINE
BUS ACTIVITY:
X24C01A
A
C
K
DATA n
DATA n+1
DATA n+2
DATA n+x
3841 FHD F14
The data output is sequential, with the data from address
n followed by the data from n + 1. The address counter
for read operations increments all address bits, allowing
the entire memory contents to be serially read during
one operation. At the end of the address space (address
127), the counter “rolls over” to address 0 and the
X24C01A continues to output data for each acknowl-
edge received. Refer to Figure 9 for the address, ac-
knowledge and data transfer sequence.
A
C
K
A
C
K
A
C
K
S
T
O
P
P
Figure 10. Typical System Configuration
VCC
SDA
SCL
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
3841 FHD F15
7
XICOR [ XICOR INC. ]
