X24F064/032/016
Block Lock Bits
The Block Lock Bits BL0 and BL1 determine which
blocks of the memory are write-protected:
Table 1. Block Lock Bits
BL1
0
0
1
1
Programmable Hardware Program Protect
The Program Protect (PP) pin and the Program Protect
Enable (PPEN) bit in the Program Protect Register
control the programmable hardware program protect
feature. Hardware program protection is enabled when
the PP pin and the PPEN bit are both
HIGH
, and
disabled when either the PP pin is LOW or the PPEN
bit is LOW. When the chip is hardware program-
protected, nonvolatile programming is disabled,
including the Program Protect Register, the BL bits and
the PPEN bit itself, as well as to Block Locked sections
in the memory array. Only the sections of the memory
array that are not Block Locked can be written. Note
that since the PPEN bit is program-protected, it cannot
be changed back to a LOW state, and program protec-
tion is disabled as long as the PP pin is held HIGH.
Table 2 defines the program protection status for each
state of PPEN and PP.
BL0
0
1
0
1
None
Array Locked
Upper 1/4
Upper 1/2
Full Array (WPR not included)
6686 FRM T02
Table 2. Program Protect Status Table
Memory Array
(Not Block Locked)
Programmable
Programmable
Programmable
PP
0
X
1
PPEN
X
0
1
Memory Array
(Block Locked)
Locked
Locked
Locked
BL Bits
Programmable
Programmable
Locked
PPEN Bit
Programmable
Programmable
Locked
6686 FRM T03
10
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