X25401
WRITE
AUTOSTORE Feature
The WRITE instruction contains the 4-bit address of
the word to be written. The write instruction is immedi-
ately followed by the 16-bit word to be written. CS must
remain LOW during the entire operation. CS must go
HIGH before the next rising edge of SCK. If CS is
brought HIGH prematurely (after the instruction but
before 16 bits of data are transferred), the instruction
register will be reset and the data that was shifted-in
will be written to RAM.
The AUTOSTORE instruction (ENAS) sets the
“AUTOSTORE enable” latch, allowing the X25401 to
automatically perform a store operation when V falls
CC
below the AUTOSTORE threshold (V
).
ASTH
WRITE PROTECTION
The X25401 provides two software write protection
mechanisms to prevent inadvertent stores of unknown
data.
Power-Up Condition
If CS is kept LOW for more than 24 SCK clock cycles
(8-bit instruction plus 16-bit data), the data already
shifted-in will be overwritten.
Upon power-up the “write enable” and “AUTOSTORE
enable” latches are in the reset state, disabling any
store operation.
READ
Unknown Data Store
The READ instruction contains the 4-bit address of the
word to be accessed. Unlike the other six instructions,
The “previous recall” latch must be set after power-up.
It may be set only by performing a software or hard-
ware recall operation, which assures that data in all
RAM locations is valid.
I of the instruction word is a “don’t care”. This provides
0
two advantages. In a design that ties both SI and SO
together, the absence of an eighth bit in the instruction
allows the host time to convert an I/O line from an
output to an input. Secondly, it allows for valid data
output during the ninth SCK clock cycle.
SYSTEM CONSIDERATIONS
Power-Up Recall
All data bits are clocked by the falling edge of SCK
(refer to Read Cycle Diagram).
The X25401 performs a power-up recall that transfers
the E PROM contents to the RAM array. Although the
2
data may be read from the RAM array, this recall does
not set the “previous recall” latch. During this power-up
recall operation, all commands are ignored. Therefore,
the host should delay any operations with the X25401
LOW POWER MODE
When CS is HIGH, non-critical internal devices are
powered-down, placing the device in the standby power
mode, thereby minimizing power consumption.
a minimum of t
after V is stable.
PUR
CC
4
XICOR [ XICOR INC. ]
