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X28C256J 参数 Datasheet PDF下载

X28C256J图片预览
型号: X28C256J
PDF下载: 下载PDF文件 查看货源
内容描述: 5伏,可变的字节E2PROM [5 Volt, Byte Alterable E2PROM]
分类和应用: 存储内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 24 页 / 114 K
品牌: XICOR [ XICOR INC. ]
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X28C256
256K
X28C256
5 Volt, Byte Alterable E
2
PROM
32K x 8 Bit
FEATURES
DESCRIPTION
The X28C256 is an 32K x 8 E
2
PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C256 is a 5V only device. The
X28C256 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs.
The X28C256 supports a 64-byte page write operation,
effectively providing a 78µs/byte write cycle and en-
abling the entire memory to be typically written in less
than 2.5 seconds. The X28C256 also features
DATA
and Toggle Bit Polling, a system software support
scheme used to indicate the early completion of a write
cycle. In addition, the X28C256 includes a user-optional
software data protection mode that further enhances
Xicor’s hardware write protect capability.
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
Access Time: 200ns
Simple Byte and Page Write
— Single 5V Supply
—No External High Voltages or V
PP
Control
Circuits
— Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS:
—Active: 60mA
—Standby: 200
µ
A
Software Data Protection
— Protects Data Against System Level
Inadvertent Writes
High Speed Page Write Capability
Highly Reliable Direct Write
Cell
— Endurance: 100,000 Write Cycles
— Data Retention: 100 Years
Early End of Write Detection
DATA
Polling
—Toggle Bit Polling
PIN CONFIGURATION
VCC
A12
A14
A13
WE
NC
A7
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X28C256
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
LCC
PLCC
TSOP
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A3
A4
A5
A6
A7
A12
A14
NC
VCC
NC
WE
A13
A8
A9
A11
OE
4
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
10
11
12
3
2
1 32 31 30
29
28
27
26
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
X28C256
X28C256
25
24
23
22
13
21
14 15 16 17 18 19 20
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
3855 ILL F23
3855 FHD F03
3855 FHD F02
© Xicor, Inc. 1991, 1995 Patents Pending
3855-1.9 8/1/97 T1/C0/D8 EW
1
Characteristics subject to change without notice