X28C64
PIN DESCRIPTIONS
Addresses (A0–A12)
Data In/Data Out (I/O0–I/O7)
Data is written to or read from the X28C64 through the
I/O pins.
The Address inputs select an 8-bit memory location
during a read or write operation.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C64.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
writeoperations.WhenCEisHIGH,powerconsumption
is reduced.
PIN CONFIGURATION
PGA
Output Enable (OE)
I/O
12
I/O
13
I/O
15
I/O
17
I/O
18
1
2
3
5
6
TheOutputEnableinputcontrolsthedataoutputbuffers
and is used to initiate read operations.
I/O
11
A
10
V
14
I/O
16
I/O
19
0
0
SS
4
7
PIN NAMES
A
A
A
A
CE
20
A
21
Symbol
A0–A12
I/O0–I/O7
WE
CE
OE
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
1
3
2
4
10
11
9
7
8
6
X28C64
OE
22
A
23
A
A
V
28
A
24
A
25
5
6
12
7
CC
9
8
5
4
2
3
A
A
NC
1
WE
27
NC
26
VCC
VSS
Ground
BOTTOM VIEW
3853 FHD F04
NC
No Connect
3853 PGM T01
FUNCTIONAL DIAGRAM
65,536-BIT
2
E PROM
X BUFFERS
LATCHES AND
DECODER
ARRAY
A –A
0
12
ADDRESS
INPUTS
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
I/O –I/O
0
7
DATA INPUTS/OUTPUTS
CE
OE
WE
CONTROL
LOGIC AND
TIMING
V
CC
V
3853 FHD F01
SS
2
XICOR [ XICOR INC. ]
