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X28C64J 参数 Datasheet PDF下载

X28C64J图片预览
型号: X28C64J
PDF下载: 下载PDF文件 查看货源
内容描述: 5伏,可变的字节E2PROM [5 Volt, Byte Alterable E2PROM]
分类和应用: 存储内存集成电路可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 25 页 / 112 K
品牌: XICOR [ XICOR INC. ]
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X28C64
64K
X28C64
5 Volt, Byte Alterable E
2
PROM
DESCRIPTION
8K x 8 Bit
FEATURES
150ns Access Time
Simple Byte and Page Write
—Single 5V Supply
—No External High Voltages or V
PP
Control
Circuits
—Self-Timed
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
Low Power CMOS
—60mA Active Current Max.
—200
µ
A Standby Current Max.
Fast Write Cycle Times
—64 Byte Page Write Operation
—Byte or Page Write Cycle: 5ms Typical
—Complete Memory Rewrite: 0.625 sec. Typical
—Effective Byte Write Cycle Time: 78
µ
s Typical
Software Data Protection
End of Write Detection
—DATA Polling
—Toggle Bit
High Reliability
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
JEDEC Approved Byte-Wide Pinout
The X28C64 is an 8K x 8 E
2
PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C64 is a 5V only device. The
X28C64 features the JEDEC approved pinout for byte-
wide memories, compatible with industry standard RAMs.
The X28C64 supports a 64-byte page write operation,
effectively providing a 78µs/byte write cycle and en-
abling the entire memory to be typically written in 0.625
seconds. The X28C64 also features
DATA
and Toggle
Bit Polling, a system software support scheme used to
indicate the early completion of a write cycle. In addi-
tion, the X28C64 includes a user-optional software data
protection mode that further enhances Xicor’s hard-
ware write protect capability.
Xicor E
2
PROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
PIN CONFIGURATION
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
X28C64
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
NC
A8
A9
A11
OE
A10
CE
I/O7
I/O6
I/O5
I/04
I/O3
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
5
6
7
8
9
10
11
12
X28C64
29
28
27
26
25
24
23
22
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
LCC
PLCC
VCC
A12
WE
NC
NC
NC
A7
TSOP
A2
A1
A0
I/O0
I/O1
I/O2
NC
VSS
NC
I/O3
I/O4
I/O5
I/O6
I/O7
CE
A10
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A3
A4
A5
A6
A7
A12
NC
NC
VCC
NC
WE
NC
A8
A9
A11
OE
4
3
2
1 32 31 30
X28C64
21
13
14 15 16 17 18 19 20
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
3853 ILL F23.1
3853 FHD F03
3853 FHD F02
© Xicor, Inc. 1991, 1995 Patents Pending
3853-2.7 4/2/96 T0/C3/D2 NS
1
Characteristics subject to change without notice