X5001
CPU Supervisor
Features
• 200ms Power On Reset Delay
• Low Vcc Detection and Reset Assertion
—Five Standard Reset Threshold Voltages
—Adjust Low Vcc Reset Threshold Voltage using
special programming sequence
—Reset Signal Valid to Vcc=1V
• Selectable Nonvolatile Watchdog Timer
—0.2, 0.6, 1.4 seconds
—Off selection
—Select settings through software
• Long Battery Life With Low Power Consumption
—<50
µ
A Max Standby Current, Watchdog On
—<1
µ
A Max Standby Current, Watchdog Off
• 2.7V to 5.5V Operation
• SPI Mode 0 interface
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Watchdog Change Latch
• High Reliability
• Available Packages
—8-Lead TSSOP
—8-Lead SOIC
—8 Pin PDIP
DESCRIPTION
This device combines three popular functions, Power on
Reset, Watchdog Timer, and Supply Voltage Supervision
in one package. This combination lowers system cost,
reduces board space requirements, and increases reli-
ability.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. During a system failure,
the device will respond with a RESET signal after a
selectable time-out interval. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
The user’s system is protected from low voltage condi-
tions by the device’s low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET is asserted until Vcc returns to proper
operating levels and stabilizes. Five industry standard
V
TRIP
thresholds are available, however, Xicor’s unique
circuits allow the thresold to be reprogrammed to meet
custom requirements or to fine-tune the threshold for
applications requiring higher precision.
The device utilizes Xicor’s proprietary Direct Write
TM
cell
for the Watchdog TImer control bits and the V
TRIP
stor-
age element, providing a minimum endurance of
100,000 write cycles and a minimum data retention of
100 years.
Block Diagram
RESET
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
SI
SO
SCK
CS/WDI
DATA
REGISTER
COMMAND
DECODE &
CONTROL
LOGIC
POWER ON/
LOW VOLTAGE
RESET
+
RESET &
WATCHDOG
TIMEBASE
V
CC
V
TRIP
GENERATION
-
7036 FRM 01
©
Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending
7078 1.1 8/9/99 CM
1
Characteristics subject to change without notice
XICOR [ XICOR INC. ]
