X5043/X5045
Figure 9. Write Memory Sequence
CS
0
SCK
Instruction
SI
8
7
6
8 Bit Address
5
3 2
Data Byte 1
5 4 3 2 1
1
2
3
4
5
6
7
8
9
10
12 13 14 15 16 17 18 19 20 21 22 23
1
0
7
6
0
9
th
Bit of Address
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Data Byte 2
5 4 3 2
Data Byte 3
5 4 3 2
Data Byte N
5 4 3 2 1
SI
7
6
1
0
7
6
1
0
6
0
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A HIGH to LOW transition on CS is required to enter
an active state and receive an instruction.
– SO pin is high impedance.
– The Write Enable Latch is reset.
– The Flag Bit is reset.
– Reset Signal is active for t
PURST
.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– A WREN instruction must be issued to set the Write
Enable Latch.
– CS must come HIGH at the proper clock count in
order to start a nonvolatile write cycle.
– Block Protect bits provide additional level of write
protection for the memory array.
– The WP pin LOW blocks nonvolatile write operations.
REV 1.1.2 5/29/01
www.xicor.com
Characteristics subject to change without notice.
9 of 20
XICOR [ XICOR INC. ]
