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X5083S8 参数 Datasheet PDF下载

X5083S8图片预览
型号: X5083S8
PDF下载: 下载PDF文件 查看货源
内容描述: CPU监控与8Kbit SPI EEPROM [CPU Supervisor with 8Kbit SPI EEPROM]
分类和应用: 电源电路电源管理电路光电二极管监控可编程只读存储器电动程控只读存储器电可擦编程只读存储器
文件页数/大小: 21 页 / 116 K
品牌: XICOR [ XICOR INC. ]
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X5083
CPU Supervisor with 8Kbit SPI EEPROM
FEATURES
• Low V
CC
detection and reset assertion
—Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
—Re-program low V
CC
reset threshold voltage
using special programming sequence.
—Reset signal valid to V
CC
= 1V
• Selectable time out watchdog timer
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<1µA max standby current, watchdog off
—<400µA max active current during read
• 8Kbits of EEPROM
• Save critical data with Block Lock
memory
—Block lock first or last page, any 1/4 or lower 1/2
of EEPROM array
• Built-in inadvertent write protection
—Write enable latch
—Write protect pin
• SPI Interface - 3.3MHz clock rate
• Minimize programming time
—16 byte page write mode
—5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages
—8-lead TSSOP, 8-lead SOIC, 8-Lead PDIP
BLOCK DIAGRAM
POR and Low
Voltage Reset
Generation
Reset & Watchdog
Timebase
Watchdog
Transition
Detector
Watchdog
Timer
Reset
APPLICATIONS
• Communications Equipment
—Routers, Hubs, Switches
—Set Top Boxes
• Industrial Systems
—Process Control
—Intelligent Instrumentation
• Computer Systems
—Desktop Computers
—Network Servers
• Battery Powered Equipment
Typical Application
2.7-5.0V
VCC
VCC
uC
X5083
RESET
CS
SCK
SI
SO
WP
VSS
10K
RESET
SPI
VSS
V
CC
V
TRIP
+
RESET (X5083)
-
X5083
Standard V
TRIP
Level
4.63V (+/-2.5%)
4.38V (+/-2.5%)
Suffix
-4.5A
-4.5
-2.7A
-2.7
CS/WDI
SI
SO
SCK
WP
Command
Decode &
Control
Logic
Protect Logic
Status
Register
EEPROM
Array
8Kbits
2.93V (+/-2.5%)
2.63V (+/-2.5%)
See “Ordering Information” on page 21 for
more details
For Custom Settings, call Xicor.
REV 1.1.6 6/25/02
www.xicor.com
Characteristics subject to change without notice.
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