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X9250US24I-2.7 参数 Datasheet PDF下载

X9250US24I-2.7图片预览
型号: X9250US24I-2.7
PDF下载: 下载PDF文件 查看货源
内容描述: 四通道数字电位器( XDCP ) [Quad Digitally Controlled Potentiometers (XDCP)]
分类和应用: 转换器电位器数字电位计电阻器光电二极管
文件页数/大小: 21 页 / 182 K
品牌: XICOR [ XICOR INC. ]
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X9250
Figure 1. Detailed Potentiometer Block Diagram
(One of Four Arrays)
Serial Data Path
From Interface
Circuitry
Register 0
8
Register 1
8
Parallel
Bus
Input
Wiper
Counter
Register
(WCR)
Serial
Bus
Input
C
o
u
n
t
e
r
D
e
c
o
d
e
V
H
/R
H
Register 2
Register 3
If WCR = 00[H] then V
W
/R
W
= V
L
/R
L
If WCR = FF[H] then V
W
/R
W
= V
H
/R
H
Inc/Dec
Logic
UP/DN
Modified SCK
UP/DN
CLK
V
L
/R
L
V
W
/R
W
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS pin goes from LOW
to HIGH after a complete write sequence is received
by the device. The progress of this internal write
operation can be monitored by a write in process bit
(WIP). The WIP bit is read with a read status
command.
INSTRUCTIONS
Identification (ID) Byte
The first byte sent to the X9250 from the host,
following a CS going HIGH to LOW, is called the
Identification byte. The most significant four bits of the
slave address are a device type identifier, for the
X9250 this is fixed as 0101[B] (refer to Figure 2).
The two least significant bits in the ID byte select one
of four devices on the bus. The physical device
address is defined by the state of the A
0
-A
1
input pins.
The X9250 compares the serial data stream with the
address input state; a successful compare of both
address bits is required for the X9250 to successfully
continue the command sequence. The A
0
–A
1
inputs
can be actively driven by CMOS input signals or tied to
V
CC
or V
SS
.
The remaining two bits in the slave byte must be set to 0.
REV 1.1.5 1/31/03
Figure 2. Identification Byte Format
Device Type
Identifier
0
1
0
1
0
0
A1
A0
Device Address
Instruction Byte
The next byte sent to the X9250 contains the
instruction and register pointer information. The four
most significant bits are the instruction. The next four
bits point to one of the four pots and, when applicable,
they point to one of four associated registers. The
format is shown below in Figure 3.
Figure 3. Instruction Byte Format
Register
Select
I3
I2
I1
I0
R1
R0
P1
P0
Instructions
Pot Select
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Characteristics subject to change without notice.
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