Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
R
Pin Description
Pins not listed are "no connects."
Table 1:
XC17S00A PROM Pinouts
8-pin
PDIP (PD8)
and
VOIC/TSOP
(VO8)
1
Pin Name
DATA
20-pin
SOIC
(SO20)
1
44-pin
VQFP
(VQ44)
40
Pin Description
Data output, High-Z state when either CE or OE are inactive.
During programming, the DATA pin is I/O. Note that OE can be
programmed to be either active High or active Low.
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
When High, this input holds the address counter reset and puts
the DATA output in a high-impedance state. The polarity of this
input pin is programmable as either RESET/OE or OE/RESET. To
avoid confusion, this document describes the pin as RESET/OE,
although the opposite polarity is possible on all devices. When
RESET is active, the address counter is held at zero, and the
DATA output is in a high-impedance state. The polarity of this input
is programmable. The default is active High RESET, but the
preferred option is active Low RESET, because it can be
connected to the FPGAs INIT pin and a pull-up resistor.
The polarity of this pin is controlled in the programmer interface.
This input pin is easily inverted using the Xilinx HW-130
programmer software. Third-party programmers have different
methods to invert this pin.
CLK
RESET/OE
(OE/RESET)
2
3
3
8
43
13
CE
4
10
15
When High, this pin resets the internal address counter, puts the
DATA output in a high-impedance state, and forces the device into
low-I
CC
standby mode.
GND is the ground connection.
The V
CC
pins are to be connected to the positive voltage supply.
GND
V
CC
5
7, 8
11
18, 20
18, 41
38, 35
2
1-800-255-7778
Advance Product Specification
XILINX [ XILINX, INC ]
