R
Spartan-II 2.5V FPGA Family: Introduction and Ordering Information
Spartan-II Product Availability
Table 2 shows the package and speed grades available for
Spartan-II family devices. Table 3 shows the maximum user
I/Os available on the device and the number of user I/Os
available for each device/package combination. The four
global clock pins are usable as additional user I/Os when
not used as a global clock pin. These pins are not included
in user I/O counts.
Table 2: Spartan-II Package and Speed Grade Availability
Pins
100
144
144
208
256
456
Plastic
VQFP
Plastic
TQFP
Chip Scale
BGA
Plastic
PQFP
Fine Pitch
BGA
Fine Pitch
BGA
Type
Code
-5
Device
VQ100
TQ144
CS144
PQ208
-
FG256
FG456
XC2S15
C, I
C, I
C
C, I
-
-
-
-
-6
C
C
-
XC2S30
XC2S50
-5
C, I
C, I
C
C, I
C, I
C
-
-
-6
C
-
C
-
-
-
-5
C, I
C
C, I
C
C, I
C
-
-6
-
-
-
XC2S100
XC2S150
XC2S200
-5
-
C, I
C
-
C, I
C
C, I
C
C, I
C
C, I
C
C, I
C
-6
-
-
-5
-
-
-
C, I
C
C, I
C
-6
-
-
-
-5
-
-
-
C, I
C
C, I
C
-6
-
-
-
Notes:
1. C = Commercial, T = 0° to +85°C; I = Industrial, TJ = –40°C to +100°C.
J
(1)
Table 3: Spartan-II User I/O Chart
Available User I/O According to Package Type
Maximum
User I/O
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
VQ100
TQ144
CS144
PQ208
-
FG256
-
FG456
86
60
60
-
86
92
92
92
-
86
92
-
-
132
176
196
260
284
132
140
140
140
140
-
-
176
176
176
176
-
-
-
196
260
284
-
-
-
-
-
Notes:
1. All user I/O counts do not include the four global clock/user input pins.
DS001-1 (v2.3) November 1, 2001
www.xilinx.com
3
Preliminary Product Specification
1-800-255-7778
XILINX [ XILINX, INC ]
